1. Technical Field
The present invention relates to a test apparatus. In particular, the present invention relates to a test apparatus that tests a device under test provided with a test function for sequentially outputting, from a single test terminal, signals that would be output from a plurality of terminals.
2. Related Art
One test for a device under test such as a semiconductor memory involves comparing a logic value output by the device under test to an expected value. For example, when testing a semiconductor memory, logic values read from the memory cells of the device under test are each compared to an expected value to judge pass/fail of each memory cell, as in, for example, Japanese Patent Application Publication No. 9-33615. At this time, the number of fails is counted for each signal terminal of the device under test to analyze how to repair the memory cells.
In order to speed up the repair analysis of the memory cells, the logic values output by the device under test can be sequentially compared to the expected value, and the number of detected fails can be sequentially counted during the testing. A test apparatus performing this process can be provided with a logic comparison circuit and a fail counter or the like for each signal terminal of the device under test.
Each logic comparison circuit may judge pass/fail by comparing the logic values read from the corresponding signal terminal to the expected value. Each fail counter may count the number of fails output by the corresponding logic comparison circuit. In this way, the number of fails for each signal terminal of the device under test can be counted, and repair analysis of the memory cells can be performed.
A known technique for decreasing the cost of the testing involves increasing the number of devices under test that are tested simultaneously. For example, by decreasing the number of pins of the test apparatus connected to a single device under test, the number of devices under test measured simultaneously can be increased without increasing the number of pins of the test apparatus.
In this case, each device under test is provided with a test function for sequentially outputting, from a single test terminal, signals that would be output from a plurality of terminals. For example, if the signal that would be output from a first signal terminal has sequential logic values of DQ1-1, DQ1-2, DQ1-3, etc. and the signal that would be output from a second signal terminal has sequential logic values of DQ2-1, DQ2-2, DQ2-3, etc., the test terminal may output a signal having sequential logic values of DQ1-1, DQ2-1, DQ1-2, DQ2-2, DQ1-3, DQ2-3, etc.
The test apparatus uses a logic comparison circuit connected to this test terminal to compare each logic value output from the test terminal to an expected value. However, the fail counter corresponding to this logic comparison circuit counts the number of fails in this logic comparison circuit, and so cannot count the number of fails separately for each signal terminal of the device under test.
In other words, the fail counter can count the total number of fails for the plurality of signal terminals corresponding to the test terminal, but cannot measure the number of fails for each individual signal terminal. Therefore, it is difficult to perform the repair analysis of the memory cells.